4 Machine Instructions

What a machine instruction represents

A Machine instruction is a binary-coded command that a processor can interpret and carry out. Assembly-language mnemonics such as ADD and LOAD are readable names for instructions; the binary encoding associated with a mnemonic depends on the processor’s design.

An Instruction set architecture (ISA) defines the instructions available to a processor, what they mean, and how their bits are organized. It is the contract that lets software instructions be interpreted by compatible processor designs.

How instruction bits are organized

An Instruction format specifies how an instruction’s bits are divided into fields. Common fields include:

• Opcode: identifies the requested operation, such as addition, loading data, or branching.

• Register fields: identify registers that supply operands or receive results.

• Operand or address field: provides a value, a memory address, or information used to calculate an address.

• Function or control fields: provide further details required by some instruction sets.

For example, a hypothetical sixteen-bit instruction could allocate four bits to an opcode, three bits to each of two register numbers, and six bits to an immediate value. This is only an illustration; real formats are determined by the ISA. Some processors use a small set of fixed-length formats, while others support multiple formats or instructions of varying lengths.

The processor decodes an instruction’s fields to determine its operation and operands. The opcode identifies the operation, while the other fields help specify which values to use and where the result may go.

How instructions locate operands

An Addressing mode determines where an operand is found or how to obtain it. The same general operation can use different modes to work with an immediate value, a register, or memory.

• Immediate: the value is written into the instruction. For example, ADD R1, #5 adds the value five to the value in R1.

• Register: the operand is held in a named processor register; an addition may use values in R1 and R2.

• Direct or absolute: the instruction contains the memory address where the operand is stored.

• Register indirect: a register contains the memory address of the operand. If R3 holds address 1000, using (R3) to load an operand reads from that location.

• Base-plus-offset (displacement): the processor adds an offset to a register value to form an address. For example, 8(R3) refers to the memory location at the address in R3 plus eight. This is useful for accessing data near a known starting address.

• PC-relative: a branch target is calculated relative to the program counter, often using a signed offset. This is useful for branches to nearby instructions.

The Effective address is the final memory address calculated by an addressing mode. Not every instruction needs to fetch an operand from data memory: an immediate operand is contained in the instruction, and a register operand is already in a register. Instruction names and syntax can vary between ISAs.

From decoded fields to results

To execute an instruction, the processor’s control circuitry acts on the decoded fields. Depending on the instruction, it may read registers, calculate an effective address, access memory, perform an arithmetic or logical operation, update status flags, write a result, or change the program counter.

For example, a load instruction reads data from memory and places it in a register. An arithmetic instruction combines its operands and writes a result. A conditional branch changes the program counter only when its condition is satisfied.

The key distinction is that decoding determines what operation and operands are requested; execution carries out that request and updates the processor’s state.

The processor’s repeating instruction cycle

The Fetch–decode–execute cycle describes how a processor repeatedly processes instructions:

1. Fetch: the Program counter (PC) identifies the address of the next instruction. The processor reads that instruction from memory into the instruction register (IR), then advances the PC. How far it advances depends on the ISA and instruction length.

2. Decode: the control unit interprets the opcode and other fields to determine the operation, operands, and addressing mode. It may obtain register values or calculate an effective address.

3. Execute: the processor carries out the operation. This may involve the arithmetic logic unit (ALU), a memory read or write, or a control-flow decision.

4. Write back and update: if the instruction produces a result, the processor stores it in the designated register or memory location. The PC proceeds to the next instruction unless a branch or another control instruction changes it.

For a load instruction, the processor fetches the instruction at the address in the PC, decodes it as a memory-to-register operation, and reads data from the effective address into the destination register. It then continues with the next instruction. Modern processors may overlap stages through pipelining while preserving the program’s defined results.

Takeaway: instruction fields describe the work and its operands; addressing modes determine how operands are found; the cycle describes how the processor repeats that work.